Test Chips Silicon Engineering Lead, Google Cloud
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience in test engineering or product engineering.
- Experience with 3 of the following: Design for Test (DFT), hardware development/design, analog or mixed-signal validation, chip packaging technology, post-silicon characterization, test engineering, Quality and Reliability (Q&R), or semiconductor manufacturing processes.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 3 years of experience with silicon products leadership.
- Experience with test hardware design and familiarity with methods for silicon qualification, such as High-Temperature Operating Life (HTOL) chambers, Electrostatic Discharge (ESD), and Latch-Up (LU).
- Experience in Fault Isolation (FI), Failure Analysis (FA), and related IC and packaging failure mechanisms.
- Experience in statistical data analysis using tools like JMP to identify commonalities and abnormalities.
- Knowledge of Quality and Reliability (Q&R) guidelines and implementation techniques.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will help to characterize technologies as preparation for Cloud products implementation. You will create products using advanced technologies, follow them into the field, and develop new test methodologies. You will examine advanced hardware to close the loop between design and testing for the next generation of chips. You will contribute to new technology development across Test, Package, Quality, High-Speed IO, and DFT. Additionally, you will require understanding of IC flows, wafer processing, testing, qualification, diagnostics, and failure analysis.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Lead the exploration of new technologies, manage silicon bring-up, and design complex Design of Experiments (DOEs).
- Manage the delivery of screening solutions for high-performance computing chips developed in advanced technology nodes.
- Design and implement industry-standard DFT best practices, including at-speed Transition Delay Fault (TDF), Scan, Memory Built-In Self-Test (MBIST), and memory repair for high-speed characterization.
- Establish and lead pre-silicon to post-silicon correlation strategies while managing technical data exchange with foundries and IP vendors.
- Design IP validation methodologies and manage the use of HVM lab equipment for complex IPs such as High-Speed SerDes, DDR/HBM, and System-Level Testing (SLT).
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