Silicon and Package SI/PI Engineer
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Minimum qualifications:
- B.Sc. degree Electrical Engineering or related field, or equivalent practical experience.
- 2 years of experience with IC package design for high speed/power ICs such as CPUs, GPUs/ASIC/Chipset.
- Experience in SI/PI design for all level interconnections including chip, package and PCB level.
- Experience in full system power analysis including silicon and package interconnect.
Preferred qualifications:
- Master's degree in Electrical Engineering or equivalent practical experience.
- Experience in electrical characterization of one or more of the following interfaces (e.g., PLL, SERDES, DDR4\5).
About the job
Our computational tests are so big, complex and unique we can't just purchase off-the-shelf hardware, we have got to make it ourselves. Our team designs and builds the hardware, software and networking technologies that power all of Google's services. In this role, you will design and build the systems that are the heart of the world's biggest computing infrastructure. You will develop from the lowest levels of circuit design to system design and see those systems all the way through to high volume manufacturing. You will have the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Own the electrical aspect of integrating advanced Physical IPs, such as PLLs, SERDES, DDR and GPIOs into our SoCs.
- Run Advanced Electrical Analysis using HSPICE\Other circuit simulators
- Generate Electrical models for chip and package co-design
- Own chip/package electrical analysis, timing, voltage and noise design budgeting and creation of package design templates, guidelines and sign-off criteria
- Drive Package trial layouts for the purpose of physical\electrical aspects investigations, and Run deep and thorough electrical analysis in the Lab using advanced measurement equipment.
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