Signoff and Circuit Methodology Engineer
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
- 5 years of experience in physical design.
- 5 years of experience in static timing analysis, circuit/signoff methodology and simulation.
- Experience in one or more sign-off convergence in Static timing analysis (STA) electrical checks and physical verification domains.
Preferred qualifications:
- Experience in using Static Timing Analysis (STA), power grid network delivery, and power analysis tools.
- Experience in timing signoff for SoCs or designs with multiple voltage/clock domains.
- Experience with Exploratory Data Analysis (EDA) tools for implementation and signoff, Physical Design, Static Timing Analysis (STA) and Electromigration and IR drop (EMIR) analysis.
- Experience in automation with programming in TCL, Python, Perl and the knowledge of Speed path debug or correlation studies.
About the job
Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities
- Work with post-silicon validation teams to improve and debug speed, Vmin and yield related issues.
- Work with cross-functional teams circuit design, physical design and sign-off methodology teams.
- Explore and specify new circuit/Static Timing Analysis methodologies for better polycrystalline silicon photovoltaic modules for low-power subsystems/System on a Chip (SoCs).
- Work with the testchip teams on process nodes to build, validate and characterize custom Internet Protocols (IPs).
- Build automation for circuit methodology, simulation and analysis.
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